I'm not going to stop poking the soldering iron to Z80, for sure, but now I want to implement 68k project.
The idea is mostly the same.
We'll boot it from AVR, sure ;-)
AVR will also always click the clocks (for stage 1) and serve as UART (for stage 1 and 2)
This is the start of desiging.
Stage 1: chips: AVR (Atmega8, I suppose, CPU (68008), SRAM chip), DTACK grounded
Stage 2: same with external quartz and the ability of cpu to turn on external quartz or switch back to AVR clock. This will be needed when we use AVR as UART. So before accessing AVR, we'll switch to AVR clock, write/read AVR, switch to fast clock.
No need to use DTACK.
SPI port. SD card.
Stage 3: same with external UART. DTACK will be grounded always except external UART accessing. So some BGERR logic is planned.
MMU is not planned, so the best I'll be able to run here is CP/M 68, not NetBSD.
[UPD error: R//W line should be inverted before going to OR to atmega; it should catch /Reads, not /Writes]
The first stage and booting logic follows:
Main program for avr -
- Hold down RESET & HALT lines, click the clock for some time.
- clock the clk line. If we have data on data line and /DS got high, put data in hi-impedance mode.
On RESET, Trigger should set 0 on Q line [/BOOTMODE], and in every read access to 0-1FFFF it will generate an INT0 on avr.
Getting the interrupt, AVR will put the byte data from the program to data line:
LEA $800,A0
LOOP: MOVE.B #$BYTE_FROM_A_PROGRAM_TO_BE_BOOTED,(A0+)
BRA LOOP
BRA $800 (and turn off the boot mode!)
(or like that)
and pausing for clicking clock until interrupt ends.
While beeing in BOOTMODE (and Q is not active) if we /write anything to 0-1FFFF the data will go to RAM. And when the bootmode ends, every access to the 0-1FFFF will go there.
Accessing D0000 - FFFFF from CPU will end boot mode. Really, now it's not clear to me should boot mode be terminated by CPU or AVR. [UPD 20140313 Later this idea was significantly simpified]
